1. Field
The present disclosure relates generally to electronic circuits, and more particularly, to network processors with multiple processing cores configurable between pipeline processing modes and parallel processing modes.
2. Background
Packet switched networks are widely used to transmit information between individuals and organizations. In packet switched networks, small blocks of information, or data packets, are transmitted over a common channel. More specifically, the information is segmented into multiple data packets at the origin and routed to the destination over the channel using an address scheme. At the destination, the information is reconstructed from the data packets.
Many devices on a network include a network processor designed to process data packets. A network processor is a software programmable device that may employ multiple processing cores. The processing cores may be dedicated in parallel, so that each data packet received by the network processor is assigned to a processing core which performs all the necessary processing on the data packet. Alternatively, the processing cores may be dedicated in a pipeline fashion, with each processing core in the pipeline dedicated to a running a specific sub-task on the data packet. Each configuration has its own advantages and disadvantages in networking applications. For example, layer 2 and layer 3 network protocols are well suited for pipelined processing, but higher layer protocols like deep packet inspection (DPI) are better suited for parallel processing. Accordingly, there is a need in the art for a single solution which efficiently supports all network protocols e.g., all layer network protocols.